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Single-Conversion DVB-H Tuner
2-Wire Serial Interface
The MAX2165 uses a 2-wire I 2 C-compatible serial inter-
face consisting of a serial-data line (SDA) and a serial-
clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX2165 and the master
at clock frequencies up to 400kHz. The master initiates
a data transfer on the bus and generates the SCL sig-
nal to permit data transfer. The MAX2165 behaves as a
slave device that transfers and receives data to and
from the master. SDA and SCL must be pulled high
with external pullup resistors (1k ? or larger) for proper
bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2165 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high peri-
od of the SCL clock pulse. Changes in SDA while SCL is
high and stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Table 20. Programmable Device Address
ADDR READ ADDRESS WRITE ADDRESS
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2165 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
Slave Address
The MAX2165 has a 7-bit slave address that must be
sent to the device following a START condition to initi-
ate communication. The slave address can be pro-
grammed to one of two possible addresses through the
ADDR pin (Table 20). The eighth bit (R/ W ) following the
7-bit address determines whether a read or write oper-
ation occurs.
The MAX2165 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/ W bit (Figure 1).
1
0
0xC3
0xC1
0xC2
0xC0
Write Cycle
When addressed with a write command, the MAX2165
allows the master to write to a single register or to multi-
I 2 C bus is a registered trademark of Philips Corp.
SLAVE ADDRESS
ple successive registers.
S
1
1
0
0
0
0
0
R/W
ACK
P
SDA
SCL
1
2
3
4
5
6
7
8
9
NOTE: TIMING PARAMETERS CONFORM WITH I 2 C BUS ? SPECIFICATIONS.
Figure 1. MAX2165 Slave Address Byte
16
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